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• Contact
• Consortium
• Objectives
• Description
  • Description of work for WP1: PDK for end-of-roadmap devices
  • Description of work for WP2: Modelling and analysis of faulty components
  • Description of work for WP3: Hardware countermeasures at the circuit level
  • Description of work for WP4: Hybrid countermeasures at the micro-architecture and system level
  • List of deliverables
• Publications
  • Project leaflets and posters
    • TRAMS leaflet 2010
    • PDK FOR SUB 16 NM TECHNOLOGY BULK MOSFETS INCLUDING STATISTICAL VARIABILITY AND STATISTICAL RELIABILITY
    • IMPACT OF VARIABILITY AND RELIABILITY ON SUB-18nm RAM MEMORIES
  • TRAMS intranet manual
  • “Controlled degradation stochastic resonance in adaptive averaging cell based architectures”
  • “Design and implementation of an adaptive proactive reconfiguration technique in SRAM caches”
  • “Capturing vulnerability variations for register files”
  • “Combining RAM technologies for hard-error recovery in L1 data caches working at very low power modes”
  • “Comparison of SRAM cells for 10nm SOI FinFETs under process and environmental variations”
  • “Impact of FinFET technology introduction in the 3T1D-DRAM memory cell”
  • “Variability mitigation mechanisms in scaled 3T1D-DRAM memories in 22nm and beyond”
  • “Efficiency Evaluation of Parametric Failure Mitigation Techiques for Reliable SRAM Operation”
  • "Software Mitigation of Transient Errors on the Single-Chip Cloud Computer"
  • “Impact bulk/SOI 10nm FinFETs on 3T1D-DRAM cell performance”
  • “A novel variation-tolerant 4T-DRAM with enhanced soft-error tolerance”
  • “Setting and error detection infrastructure with low cost acoustic wave detectors”
  • “Analysis of FinFET technology on memories"
  • “Fault-tolerant nanoscale architecture based on linear threshold gates with redundancy”
  • “Modified Berger codes for on-line DRAM repair strategies”
  • “Adaptive fault-tolerant architecture for unreliable technologies with heterogeneous variability”
  • “Statistical variability stydy of extreme-scaled SOI Fin-FET devices”
  • “Variability and reliability analysis of CNFET in the presence of carbon nanotube density fluctuations”
  • “SRAM lifetime improvement by using adaptive proactive reconfiguration”
  • “Process variability-aware proactive reconfiguration techniques for mitigating aging in nano scale SRAM lifetime”
  • “Degradation Stochastic Resonance (DSR) in AD-AVG architectures”
  • “DFH(eterogeneity) for tera-scale reliable processors”
  • “Mitigating lower layer failures with adaptive system reconfiguration”
  • “Enhancing 6T SRAM cell stability by back gate biasing techniques for 10nm SOI Finfets under process and environmental variations”
  • “Strain relevance on the improvement of the 3T1D cell performance”
  • “New redundant logic design concept for high noise and low voltage scenarios”
  • “Impact of positive bias temperatura instability (PBTI) on 3T1D-DRAM cells”
  • “Impact of positive temperature instability on 3T1D DRAM cells integration”
  • “Statistical Variability and Reliability in Nanoscale FinFETs”
  • “Transient noise failures SRAM cells dynamic metric”
  • “Dynamic Fine-Grain Body Biasing of Caches with Latency and Leakage 3T1D-Based Monitors”
  • "Challenges in Computing in the Age of Heterogeneous Computing"
  • "Statistical threshold-voltage variability in scaled decananometer bulk HKMG MOSFETs: a full-scale 3D simulation scaling study"
  • “A comparative variability analysis for CMOS and CNTFET 6T SRAM cells”
  • “Carbon nanotube growth process-related variability in CNFETs”
  • “Adaptive Fault-Tolerant Architecture for Unreliable Device Technologies”
  • “TRAMS: Variability as a limiting factor of energy efficiency”
  • "Low Power Microarchitectures, tools for power/reliability simulation/estimation"
  • "Variability and technology aware SRAM Product yield maximization"
  • “Device Variability Analysis in Carbon Nanotube Technology”
  • “DEVICE TO PRODUCT LEVEL ASSESSMENT OF PROCESS VARIABILITY”
  • “TRAMS : Terascale reliable adaptive memory systems”
  • “Statistical Analysis of 6T SRAM Data Retention Voltage under Process Variation”
  • "Invited talk at HiPEAC Computing SystemsWeek, Task Force on Reliability and Availability"
  • "Manufacturing Variability Analysis in Carbon Nanotube Technology: comparison with bulk CMOS in 6T SRAM scenario"
  • “Drain current collapse in nanoscaled bulk MOSFETs due to random dopant compensation in the source/drain extensions”
  • “Variability aware modelling for yield enhancement of SRAM and logic"
  • “Statistical aspects of NBTI/PBTI and impact on SRAM yield”
  • “A new probabilistic design methodology of nanoscale digital circuits”
  • "Runtime Monitoring of Power/Performance of Caches under Variability using Embedded 3T1D Cells”
  • "Robustness Analysis of 6T SRAMs in Memory Retention Mode under PVT Variations"
  • “Analysis of the mismatch of digital circuits by common environment fluctuations”
  • "New reliability mechanisms in memory design for sub-22nm technologies”
  • “Unidirectional error detection, localization and correction for DRAMs: Application to on-line DRAM repair strategies”
  • “Fault Tolerant Nanoscale Architecture based on Linear Threshold gates, with redundancy”
  • "Robustness of SRAM to Power Supply Noise during Leakage Power Saving in DVS"
  • “Design of Boolean functions and memory units based on Resistive Switching devices”
  • “Impact of metal gate granularity on the statistical variability in scaled decananometre bulk MOSFETs: A full-scale 3D simulation study”
  • “Simulation of statistical variability in 18 and 13nm bulk MOSFETs”
  • “Electronic design paradigms in the technologies of the year 2020”
  • "TCAD simulation of statistical variability"
  • "Cache Design Under Spatio-Temporal Variability"
  • "MODEST : A Model for Energy Estimation under Spatio-Temporal Variability"
  • “A comprehensive compensation technique for process variations and environmental fluctuations in digital integrated circuits”
  • ”Turtle Logic: a new design metholodology of nanoscale digital circuits”
  • ”Turtle: a new design metholodology for high noise low signal level scenarios.”
  • “A holistic approach for statistical analysis of SRAM”
  • “Statistical SRAM analysis for yield enhancement”
  • "Circuit Propagation Delay Estimation Through Multivariate Regression-Based Modeling Under Spatio-Temporal Variability"
  • "Parametric Failure Analysis of Embedded SRAMs using Fast & Accurate Dynamic Analysis"
  • "Statistical Analysis of SRAM Parametric Failure under Supply Voltage Scaling"
• Public deliverables
  • Deliverable 5.1. TRAMS PROJECT WEBSITE DESCRIPTION
  • Deliverable 5.2. Dissemination, use plan and join collaborative actions
  • Publishable summary activities during first year (Y1)
  • Deliverable D1.2 PDK for sub 16 nm CNT transistors including statistical variability and reliability
    • Deliverable D1.2 PDK for sub 16 nm CNT transistors including statistical variability and reliability
  • Deliverable D4.2.1 Report of the mechanisms devised to reconfigure each memory block
    • D4.2.1 Report of the mechanisms devised to reconfigure each memory block
  • D5.3 Dissemination, Use Plan and Joint collaborative actions (Y2)
    • D5.3 Dissemination, Use Plan and Joint collaborative actions (Y2)
  • Publishable summary activities during second year (Y2)
    • Publishable summary activities during second year (Y2)
  • D2.3 Report on assessment of III-V/Ge and CNT technologies (Y3)
  • D4.2.2 Report of the mechanisms devised to reconfigure each memory block (Y3)
  • D4.3.2 Report on the proposed hybrid countermeasures including a complete specification (Y3)
  • D5.4 Final dissemination, use plan and joint collaborative actions (Y3)
  • D6.4 Final consolidated report (Y3)
  • D6.5 Gender aspects report (Y3)
  • Publishable summary (Y3)
  • Final Report
• Intranet
  • PMB and PTC meetings and documents
    • Kickoff agenda, February 1st 2010
    • Kickoff presentation, February 1st 2010
    • Kickoff conclusions, February 1st 2010
    • Project Changes Proposal, March 2010
    • Detailed Proposed Changes, March 2010
    • Reviewed Dow, March 2010
    • PMB Meeting in Brussels, June 28th 2010
    • PTC Meeting July 9th 2010
    • PTC meeting November 3rd, 2010
    • PMB Meeting in Barcelona, December 14th 2010
    • PMB and PTC meeting at DATE conference, March 15th 2011
    • PTC meeting June 23rd 2011
    • PMB Meeting Glasgow Septemebr 9th 2011
    • PTC meeting November 2011
    • PMB Meeting M25 Barcelona January 31st 2012
    • PMB meeting M34, Leuven March 12th 2012
  • PMB planned actions
    • Press Release, February 23rd 2010
    • Project Brochure
    • EP booth at DATE 2011
  • Internal documents by Workpackages
    • Workpackage 1
    • Workpackage 2
    • Workpackage 3
    • Workpackage 4
    • Workpackage 5
    • Workpackage 6
  • Reviewer's area
    • Deliverables for first year (Y1)
    • Agenda Project Review Meeting April 12th 2011
    • PPT slides First Year Project Review Meeting
    • Original DoW (2010)
    • Amended DoW after Y1 review meeting (dated 2011)
    • Document comparing DoWs in NEF and Amended
    • Deliverables second year (Y2)
    • Deliverables for third year (Y3)
    • Agenda Project Review Meeting Y2 (April 16th 2012)
    • Agenda Project Review Meeting Y3 (March 26th 2013)
  • TRAMS intranet manual
  • Consortium agreement
  • DoW TRAMS Project
    • Original DoW as it is in the NEF (dated 2009)
    • Amended DoW after Y1 review meeting (dated 2011)
    • Detailed comparison between Original in DoW and Amended
  • Internal Workshop, Glasgow 2011
    • Summary of presentations including agenda
    • Photography
• CASTNESS'13