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Description of work for WP1: PDK for end-of-roadmap devices


   It is however inevitable that at sub-10 nm dimensions statistical variability and reliability of the above devices will be the major challenge in their tera-memory integration. Random discrete dopants and atomic scale interface roughness in sub 10 nm nanowire transistors will result in dramatic threshold voltage and on current variation. In addition single charge trapping associated with NBTI, PBTI or hot carrier degradation can result in memory intolerable threshold voltage changes.

Fig_WP1_2.1.jpg

 Variability in nanovire transistors: interface roughness and random dopants. Potential.

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 Vertically integrated nanowire transistors. Current

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 Impact of single trapped charge on VT of a 2.2x2.2x6nm nanowire transistor: DD vs NEGF.


   The first step in the process of creating the PDK is the TCAD design of target transistors with memory worthy characteristics in terms of threshold voltage, drive and leakage current. The TCAD tools will be calibrated in respect of accurate but expensive 3D Monte Carlo and quantum transport simulators developed at UOG. The device design and the results from the TCAD simulations will be used to establish basic design rules for each particular type of devices that will be used to lay out the memory cell and periphery.

   The results of the TCAD simulations using continuous doping and smooth interfaces will be used to extract nominal compact models. The intention is to use industrial standard compact models like BSIM and PSP but some adaptation will be needed to match the characteristics of the nanowire and III-V/Ge MOSFETs.

   The statistical variability of ‘fresh’ devices will be simulated using the UOG 3D atomistic statistical simulator combating DD, MC and NEGF simulation techniques. The results will be captured in statistical compact models using technology developed at UOG and IMEC.

   Analytical models developed at IMEC will be used to trace the dynamics of the areal density of trapped charge in the relevant gates stacks as a result of NBTI, PBTI and hot carrier degradation. The statistical impact of this trapped charge on the evolution of the statistical distribution of the device characteristics and the statistical aspects of the the soft gate oxide breakdown will be simulated by combining the underlying sources of statistical variability and the random position of trapped charges and defects in the gate stack. The results will be captured in time evolving compact models.

   Finally an approximation for the technology filed that contains information about the interconnects will be needed. This will be done on the basis of a careful estimate of the technology options at the estimated time of insertion of the investigated devices in mass production. We anticipate return to Al for the first 1-2 layers of interconnect in combination of air gaps. Comprehensive 3D physical simulations of the anticipated interconnect solutions will be followed by extraction of simplified RC models of interconnects for the technology files.