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Publications

Project leaflets and posters
TRAMS intranet manual
“Controlled degradation stochastic resonance in adaptive averaging cell based architectures”
N. Aymerich, S. Cotofana, A. Rubio, “Controlled degradation stochastic resonance in adaptive averaging cell based architectures”, IEEE Transactions on Nanotechnology (invited, accepted), 2013.
“Design and implementation of an adaptive proactive reconfiguration technique in SRAM caches”
P. Pouyan, E. Amat, A. Rubio, “Design and implementation of an adaptive proactive reconfiguration technique in SRAM caches”, DATE 2013 (accepted)
“Capturing vulnerability variations for register files”
J. Carretero, E. Herrero, M. Monchiero, T. Ramirez, X. Vera, “Capturing vulnerability variations for register files”, DATE 2013 (accepted)
“Combining RAM technologies for hard-error recovery in L1 data caches working at very low power modes”
V. Lorente et al., “Combining RAM technologies for hard-error recovery in L1 data caches working at very low power modes”, DATE 2013 (accepted)
“Comparison of SRAM cells for 10nm SOI FinFETs under process and environmental variations”
Z. Jaksic, R. Canal, “Comparison of SRAM cells for 10nm SOI FinFETs under process and environmental variations”, IEEE Transactions on Electron Devices, vol.6, no.1, pp. 49-55, January 2013. DOI: 10.1109/TED.2012.2226095
“Impact of FinFET technology introduction in the 3T1D-DRAM memory cell”
E. Amat et al., “Impact of FinFET technology introduction in the 3T1D-DRAM memory cell”, submitted to IEEE Transactions on Devices and Materials Reliability. DOI: 10.1109/TDMR.2013.2238542
“Variability mitigation mechanisms in scaled 3T1D-DRAM memories in 22nm and beyond”
E. Amat, et al., “Variability mitigation mechanisms in scaled 3T1D-DRAM memories in 22nm and beyond”, IEEE Transactions on Devices and Materials Reliability, (accepted) 2013. DOI: 10.1109/TDMR.2012.2217497
“Efficiency Evaluation of Parametric Failure Mitigation Techiques for Reliable SRAM Operation”
E. I. Vatajelu, J. Figueras, “Efficiency Evaluation of Parametric Failure Mitigation Techiques for Reliable SRAM Operation”, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012, pp. 1343-1348. DOI: 10.1109/DATE.2012.6176700
"Software Mitigation of Transient Errors on the Single-Chip Cloud Computer"
D. Rodopoulos, A. Papanikolaou and F. Catthoor, "Software Mitigation of Transient Errors on the Single-Chip Cloud Computer", in IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE), Urbana-Champaign, IL, US, 2012.
“Impact bulk/SOI 10nm FinFETs on 3T1D-DRAM cell performance”
E. Amat et al., “Impact bulk/SOI 10nm FinFETs on 3T1D-DRAM cell performance” 11th IEEE Int. Conf. on Solid-State and Integrated Circuits Technology (ICSICT), 2012, Xi’an, China.
“A novel variation-tolerant 4T-DRAM with enhanced soft-error tolerance”
S. Ganapathy, R. Canal, D. Alexandrescu, E. Costenaro, A. Gonzalez, A. Rubio, “A novel variation-tolerant 4T-DRAM with enhanced soft-error tolerance”, ICCD 2012, pp. 472-477. DOI: 10.1109/ICCD.2012.6378681
“Setting and error detection infrastructure with low cost acoustic wave detectors”
G. Upasani, X. Vera, A. Gonzalez, “Setting and error detection infrastructure with low cost acoustic wave detectors”, International Symposium on Computer Architecture (ISCA 2012), pp. 333-343. DOI: 10.1145/2366231.2337198
“Analysis of FinFET technology on memories"
E. Amat, et al., “Analysis of FinFET technology on memories", IEEE Int. On-line Test Symposium, p. 169, 2012, p. 169. DOI: 10.1109/IOLTS.2012.6313866
“Fault-tolerant nanoscale architecture based on linear threshold gates with redundancy”
N. Aymerich, R.Canal, A.Gonzalez, A. Rubio, “Fault-tolerant nanoscale architecture based on linear threshold gates with redundancy” Microprocessors and Microprosystems, volumen 36, issue 5, July 2012, pp. 420-426, DOI 10.1016/j.micpro.2012.02.003
“Modified Berger codes for on-line DRAM repair strategies”
M. Neagu, L. Miclea, “Modified Berger codes for on-line DRAM repair strategies”, IEEE AQTR, 2012, pp. 296-301. May 2012. DOI: 10.1109/AQTR.2012.6237720
“Adaptive fault-tolerant architecture for unreliable technologies with heterogeneous variability”
N. Aymerich, S. Corin and A. Rubio, “Adaptive fault-tolerant architecture for unreliable technologies with heterogeneous variability”, IEEE Transaction on Nanotechnology, volumen 11, issue 4, pp. 818-829, May 2012, DOI 10.1109/TNANO.2012.2199513
“Statistical variability stydy of extreme-scaled SOI Fin-FET devices”
B. Cheng, A.R. Brown, X. Wang, A. ASenov, “Statistical variability stydy of extreme-scaled SOI Fin-FET devices”, Silicon Nanoelectronics Workshop, Honolulu, June 10-11, pp. 69-70, 2012. DOI: 10.1109/SNW.2012.6243343
“Variability and reliability analysis of CNFET in the presence of carbon nanotube density fluctuations”
C. García, A. Rubio, “Variability and reliability analysis of CNFET in the presence of carbon nanotube density fluctuations”, Proceedings of the MIXDES Conference, 2012, 24th-26th May, Warsaw,pp.124-129. ISBN 978-1-4577-2092-5 (IEEE Xplore)