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Publications

“SRAM lifetime improvement by using adaptive proactive reconfiguration”
P. Peyman et al., “SRAM lifetime improvement by using adaptive proactive reconfiguration”, MIXDES 2012, 24th-26th May, Warsaw, pp. 115-119. ISBN 978-1-4577-2092-5 (IEEE Xplore)
“Process variability-aware proactive reconfiguration techniques for mitigating aging in nano scale SRAM lifetime”
P. Peyman, A. Rubio, “Process variability-aware proactive reconfiguration techniques for mitigating aging effects in nano scale SRAM lifetime”, IEEE VLSI Test Symposium (VTS), Hawaii, May 2012, pp.240-245. DOI: 10.1109/VTS.2012.6231060
“Degradation Stochastic Resonance (DSR) in AD-AVG architectures”
N. Aymerich, S. Cotofana, A. Rubio, “Degradation Stochastic Resonance (DSR) in AD-AVG architectures”, IEEE Nano 2012, Birmingham, 2012, pp. 1-4. DOI: 10.1109/NANO.2012.6321971
“DFH(eterogeneity) for tera-scale reliable processors”
X. Vera, “DFH(eterogeneity) for tera-scale reliable processors”, IEEE LSI Test Symposium (VTS), Hawaii, May 2012. DOI: 10.1109/VTS.2012.6231108
“Mitigating lower layer failures with adaptive system reconfiguration”
T. Ramírez at al., “Mitigating lower layer failures with adaptive system reconfiguration” MIXDES 2012, 24th-26th May, Warsaw. ISBN 978-1-4577-2092-5 (IEEE Xplore)
“Enhancing 6T SRAM cell stability by back gate biasing techniques for 10nm SOI Finfets under process and environmental variations”
Z. Jaksic et al., “Enhancing 6T SRAM cell stability by back gate biasing techniques for 10nm SOI Finfets under process and environmental variations”, MIXDES 2012, 24th-26th May, Warsaw, pp. 103-108. ISBN 978-1-4577-2092-5 (IEEE Xplore)
“Strain relevance on the improvement of the 3T1D cell performance”
E. Amat, et al., “Strain relevance on the improvement of the 3T1D cell performance” MIXDES 2012, 24th-26th May, Warsaw. pp. 120-123. ISBN 978-1-4577-2092-5 (IEEE Xplore)
“New redundant logic design concept for high noise and low voltage scenarios”
L. García-Leyva., et al., “New redundant logic design concept for high noise and low voltage scenarios”, Microelectronics Journal, 42 (2011), pp. 1359-1369. DOI: 10.1016/j.mejo.2011.09.007
“Impact of positive bias temperatura instability (PBTI) on 3T1D-DRAM cells”
N. Aymerich, S. Ganapathy, A. Rubio, R. Canal, A. González, “Impact of positive bias temperatura instability (PBTI) on 3T1D-DRAM cells”, IEEE/ACM Great Lakes Symposium on VLSI, Lausanne (Switzerland), May 2011. DOI 10.1016/j.vlsi.2011.11.014
“Impact of positive temperature instability on 3T1D DRAM cells integration”
N. Nivard, R. Canal, A. Gonzalez, A. Rubio, “Impact of positive temperature instability on 3T1D DRAM cells integration”, VLSI Journal Integration, 45-3, pp. 246-252, 2012. DOI: 10.1016/j.vlsi.2011.11.014
“Statistical Variability and Reliability in Nanoscale FinFETs”
X. Wang, A. R. Brown, B. Cheng and A. Asenov, “Statistical Variability and Reliability in Nanoscale FinFETs”, International Electron Devices Meeting (IEDM), Washington D.C., December 2011, pp. 5.4.1-5.4.4. DOI: 10.1109/IEDM.2011.6131494
“Transient noise failures SRAM cells dynamic metric”
I. Vatajelu, J, Figueras, “Transient noise failures SRAM cells dynamic metric”, IEEE Asian Test Symposium, New Delhi, 2011, pp. 413-418. DOI: 10.1109/ATS.2011.64
“Dynamic Fine-Grain Body Biasing of Caches with Latency and Leakage 3T1D-Based Monitors”
S. Ganapathy, R. Canal, A. González, A. Rubio. “Dynamic Fine-Grain Body Biasing of Caches with Latency and Leakage 3T1D-Based Monitors”. 29th IEEE International Conference on Computer Design (ICCD'11), Amherst (MA, USA), October 2011, pp. 332-338. DOI: 10.1109/ICCD.2011.6081420
"Challenges in Computing in the Age of Heterogeneous Computing"
"Challenges in Computing in the Age of Heterogeneous Computing" 29th IEEE International Conference on Computer Design (ICCD'11), Amherst (MA, USA), October 2011
"Statistical threshold-voltage variability in scaled decananometer bulk HKMG MOSFETs: a full-scale 3D simulation scaling study"
X. Wang, A. R. Brown, N. M. Idris, S. Markov, G. Roy, and A. Asenov, "Statistical threshold-voltage variability in scaled decananometer bulk HKMG MOSFETs: A full-scale 3-D simulation scaling study". IEEE Transactions on Electron Devices, Vol. 58, No. 8, pp. 2293–2301, 2011. DOI: 10.1109/TED.2011.2149531
“A comparative variability analysis for CMOS and CNTFET 6T SRAM cells”
C. García and A. Rubio, “A comparative variability analysis for CMOS and CNTFET 6T SRAM cells”, IEEE Int. Midwest Symp. on Circuits and Systems (MWSCAS), pp.1-4, Seoul August 2011. DOI: 10.1109/MWSCAS.2011.6026572
“Carbon nanotube growth process-related variability in CNFETs”
C. García and A. Rubio, “Carbon nanotube growth process-related variability in CNFETs”, IEEE NANO 2011, August 15-19, pp- 1084-1087, Portland, Oregon. DOI: 10.1109/NANO.2011.6144375
“Adaptive Fault-Tolerant Architecture for Unreliable Device Technologies”
N. Aymerich, S. Cotofana, A. Rubio, “Adaptive Fault-Tolerant Architecture for Unreliable Device Technologies”, IEEE NANO 2011, August 15-19, pp. 1441-1444, Portland, Oregon. DOI: 10.1109/NANO.2011.6144528
“TRAMS: Variability as a limiting factor of energy efficiency”
A.Rubio, A. Asenov. “TRAMS: Variability as a limiting factor of energy efficiency”, Workshop on Energy Efficient Systems, Barcelona, July 18th, 2011.
"Low Power Microarchitectures, tools for power/reliability simulation/estimation"
Summer school, lecturer "Low Power Microarchitectures, tools for power/reliability simulation/estimation" ARCHI'11 (École thématique), Mont-Louis, France, June 2011