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D2 1_TRAMS_v3.0 (pdf)

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The focus of this deliverable is a method to enable design-phase assessment of statistical stability and performance metrics of full memory arrays under variability degradation due to aging conditions. The method is based on existing imec background for statistical SRAM analysis [17]. Specific extensions needed to perform statistical analysis under variability degradation conditions are explicitly considered and reported within this deliverable. Such extensions aim at providing statistical information on current/voltages, timing, power of selected internal signals of the circuit netlist and yield related information under conditions of variability degradation, solely originated from device aging effects. All other analysis conditions related to process variation impact at manufacturing time remain within the scope mentioned above. In addition, this deliverable also reports industrial-grade SRAM design at the TRAMS technology nodes agreed for the first period of the project (e.g., bulk CMOS 18 and 13nm technologies) and it provides application results of the above methods under the example of these test vehicles.

D2 1_TRAMS_v3.0.pdf — PDF document, 1186 kB (1214656 bytes)

last modified : February 2011
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