# Publications

- Project leaflets and posters
- TRAMS intranet manual
- “Controlled degradation stochastic resonance in adaptive averaging cell based architectures”
- N. Aymerich, S. Cotofana, A. Rubio, “Controlled degradation stochastic resonance in adaptive averaging cell based architectures”, IEEE Transactions on Nanotechnology (invited, accepted), 2013.
- “Design and implementation of an adaptive proactive reconfiguration technique in SRAM caches”
- P. Pouyan, E. Amat, A. Rubio, “Design and implementation of an adaptive proactive reconfiguration technique in SRAM caches”, DATE 2013 (accepted)
- “Capturing vulnerability variations for register files”
- J. Carretero, E. Herrero, M. Monchiero, T. Ramirez, X. Vera, “Capturing vulnerability variations for register files”, DATE 2013 (accepted)
- “Combining RAM technologies for hard-error recovery in L1 data caches working at very low power modes”
- V. Lorente et al., “Combining RAM technologies for hard-error recovery in L1 data caches working at very low power modes”, DATE 2013 (accepted)
- “Comparison of SRAM cells for 10nm SOI FinFETs under process and environmental variations”
- Z. Jaksic, R. Canal, “Comparison of SRAM cells for 10nm SOI FinFETs under process and environmental variations”, IEEE Transactions on Electron Devices, vol.6, no.1, pp. 49-55, January 2013. DOI: 10.1109/TED.2012.2226095
- “Impact of FinFET technology introduction in the 3T1D-DRAM memory cell”
- E. Amat et al., “Impact of FinFET technology introduction in the 3T1D-DRAM memory cell”, submitted to IEEE Transactions on Devices and Materials Reliability. DOI: 10.1109/TDMR.2013.2238542
- “Variability mitigation mechanisms in scaled 3T1D-DRAM memories in 22nm and beyond”
- E. Amat, et al., “Variability mitigation mechanisms in scaled 3T1D-DRAM memories in 22nm and beyond”, IEEE Transactions on Devices and Materials Reliability, (accepted) 2013. DOI: 10.1109/TDMR.2012.2217497
- “Efficiency Evaluation of Parametric Failure Mitigation Techiques for Reliable SRAM Operation”
- E. I. Vatajelu, J. Figueras, “Efficiency Evaluation of Parametric Failure Mitigation Techiques for Reliable SRAM Operation”, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012, pp. 1343-1348. DOI: 10.1109/DATE.2012.6176700
- "Software Mitigation of Transient Errors on the Single-Chip Cloud Computer"
- D. Rodopoulos, A. Papanikolaou and F. Catthoor, "Software Mitigation of Transient Errors on the Single-Chip Cloud Computer", in IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE), Urbana-Champaign, IL, US, 2012.
- “Impact bulk/SOI 10nm FinFETs on 3T1D-DRAM cell performance”
- E. Amat et al., “Impact bulk/SOI 10nm FinFETs on 3T1D-DRAM cell performance” 11th IEEE Int. Conf. on Solid-State and Integrated Circuits Technology (ICSICT), 2012, Xi’an, China.
- “A novel variation-tolerant 4T-DRAM with enhanced soft-error tolerance”
- S. Ganapathy, R. Canal, D. Alexandrescu, E. Costenaro, A. Gonzalez, A. Rubio, “A novel variation-tolerant 4T-DRAM with enhanced soft-error tolerance”, ICCD 2012, pp. 472-477. DOI: 10.1109/ICCD.2012.6378681
- “Setting and error detection infrastructure with low cost acoustic wave detectors”
- G. Upasani, X. Vera, A. Gonzalez, “Setting and error detection infrastructure with low cost acoustic wave detectors”, International Symposium on Computer Architecture (ISCA 2012), pp. 333-343. DOI: 10.1145/2366231.2337198
- “Analysis of FinFET technology on memories"
- E. Amat, et al., “Analysis of FinFET technology on memories", IEEE Int. On-line Test Symposium, p. 169, 2012, p. 169. DOI: 10.1109/IOLTS.2012.6313866
- “Fault-tolerant nanoscale architecture based on linear threshold gates with redundancy”
- N. Aymerich, R.Canal, A.Gonzalez, A. Rubio, “Fault-tolerant nanoscale architecture based on linear threshold gates with redundancy” Microprocessors and Microprosystems, volumen 36, issue 5, July 2012, pp. 420-426, DOI 10.1016/j.micpro.2012.02.003
- “Modified Berger codes for on-line DRAM repair strategies”
- M. Neagu, L. Miclea, “Modified Berger codes for on-line DRAM repair strategies”, IEEE AQTR, 2012, pp. 296-301. May 2012. DOI: 10.1109/AQTR.2012.6237720
- “Adaptive fault-tolerant architecture for unreliable technologies with heterogeneous variability”
- N. Aymerich, S. Corin and A. Rubio, “Adaptive fault-tolerant architecture for unreliable technologies with heterogeneous variability”, IEEE Transaction on Nanotechnology, volumen 11, issue 4, pp. 818-829, May 2012, DOI 10.1109/TNANO.2012.2199513
- “Statistical variability stydy of extreme-scaled SOI Fin-FET devices”
- B. Cheng, A.R. Brown, X. Wang, A. ASenov, “Statistical variability stydy of extreme-scaled SOI Fin-FET devices”, Silicon Nanoelectronics Workshop, Honolulu, June 10-11, pp. 69-70, 2012. DOI: 10.1109/SNW.2012.6243343
- “Variability and reliability analysis of CNFET in the presence of carbon nanotube density fluctuations”
- C. García, A. Rubio, “Variability and reliability analysis of CNFET in the presence of carbon nanotube density fluctuations”, Proceedings of the MIXDES Conference, 2012, 24th-26th May, Warsaw,pp.124-129. ISBN 978-1-4577-2092-5 (IEEE Xplore)
- “SRAM lifetime improvement by using adaptive proactive reconfiguration”
- P. Peyman et al., “SRAM lifetime improvement by using adaptive proactive reconfiguration”, MIXDES 2012, 24th-26th May, Warsaw, pp. 115-119. ISBN 978-1-4577-2092-5 (IEEE Xplore)
- “Process variability-aware proactive reconfiguration techniques for mitigating aging in nano scale SRAM lifetime”
- P. Peyman, A. Rubio, “Process variability-aware proactive reconfiguration techniques for mitigating aging effects in nano scale SRAM lifetime”, IEEE VLSI Test Symposium (VTS), Hawaii, May 2012, pp.240-245. DOI: 10.1109/VTS.2012.6231060
- “Degradation Stochastic Resonance (DSR) in AD-AVG architectures”
- N. Aymerich, S. Cotofana, A. Rubio, “Degradation Stochastic Resonance (DSR) in AD-AVG architectures”, IEEE Nano 2012, Birmingham, 2012, pp. 1-4. DOI: 10.1109/NANO.2012.6321971
- “DFH(eterogeneity) for tera-scale reliable processors”
- X. Vera, “DFH(eterogeneity) for tera-scale reliable processors”, IEEE LSI Test Symposium (VTS), Hawaii, May 2012. DOI: 10.1109/VTS.2012.6231108
- “Mitigating lower layer failures with adaptive system reconfiguration”
- T. Ramírez at al., “Mitigating lower layer failures with adaptive system reconfiguration” MIXDES 2012, 24th-26th May, Warsaw. ISBN 978-1-4577-2092-5 (IEEE Xplore)
- “Enhancing 6T SRAM cell stability by back gate biasing techniques for 10nm SOI Finfets under process and environmental variations”
- Z. Jaksic et al., “Enhancing 6T SRAM cell stability by back gate biasing techniques for 10nm SOI Finfets under process and environmental variations”, MIXDES 2012, 24th-26th May, Warsaw, pp. 103-108. ISBN 978-1-4577-2092-5 (IEEE Xplore)
- “Strain relevance on the improvement of the 3T1D cell performance”
- E. Amat, et al., “Strain relevance on the improvement of the 3T1D cell performance” MIXDES 2012, 24th-26th May, Warsaw. pp. 120-123. ISBN 978-1-4577-2092-5 (IEEE Xplore)
- “New redundant logic design concept for high noise and low voltage scenarios”
- L. García-Leyva., et al., “New redundant logic design concept for high noise and low voltage scenarios”, Microelectronics Journal, 42 (2011), pp. 1359-1369. DOI: 10.1016/j.mejo.2011.09.007
- “Impact of positive bias temperatura instability (PBTI) on 3T1D-DRAM cells”
- N. Aymerich, S. Ganapathy, A. Rubio, R. Canal, A. González, “Impact of positive bias temperatura instability (PBTI) on 3T1D-DRAM cells”, IEEE/ACM Great Lakes Symposium on VLSI, Lausanne (Switzerland), May 2011. DOI 10.1016/j.vlsi.2011.11.014
- “Impact of positive temperature instability on 3T1D DRAM cells integration”
- N. Nivard, R. Canal, A. Gonzalez, A. Rubio, “Impact of positive temperature instability on 3T1D DRAM cells integration”, VLSI Journal Integration, 45-3, pp. 246-252, 2012. DOI: 10.1016/j.vlsi.2011.11.014
- “Statistical Variability and Reliability in Nanoscale FinFETs”
- X. Wang, A. R. Brown, B. Cheng and A. Asenov, “Statistical Variability and Reliability in Nanoscale FinFETs”, International Electron Devices Meeting (IEDM), Washington D.C., December 2011, pp. 5.4.1-5.4.4. DOI: 10.1109/IEDM.2011.6131494
- “Transient noise failures SRAM cells dynamic metric”
- I. Vatajelu, J, Figueras, “Transient noise failures SRAM cells dynamic metric”, IEEE Asian Test Symposium, New Delhi, 2011, pp. 413-418. DOI: 10.1109/ATS.2011.64
- “Dynamic Fine-Grain Body Biasing of Caches with Latency and Leakage 3T1D-Based Monitors”
- S. Ganapathy, R. Canal, A. González, A. Rubio. “Dynamic Fine-Grain Body Biasing of Caches with Latency and Leakage 3T1D-Based Monitors”. 29th IEEE International Conference on Computer Design (ICCD'11), Amherst (MA, USA), October 2011, pp. 332-338. DOI: 10.1109/ICCD.2011.6081420
- "Challenges in Computing in the Age of Heterogeneous Computing"
- "Challenges in Computing in the Age of Heterogeneous Computing" 29th IEEE International Conference on Computer Design (ICCD'11), Amherst (MA, USA), October 2011
- "Statistical threshold-voltage variability in scaled decananometer bulk HKMG MOSFETs: a full-scale 3D simulation scaling study"
- X. Wang, A. R. Brown, N. M. Idris, S. Markov, G. Roy, and A. Asenov, "Statistical threshold-voltage variability in scaled decananometer bulk HKMG MOSFETs: A full-scale 3-D simulation scaling study". IEEE Transactions on Electron Devices, Vol. 58, No. 8, pp. 2293–2301, 2011. DOI: 10.1109/TED.2011.2149531
- “A comparative variability analysis for CMOS and CNTFET 6T SRAM cells”
- C. García and A. Rubio, “A comparative variability analysis for CMOS and CNTFET 6T SRAM cells”, IEEE Int. Midwest Symp. on Circuits and Systems (MWSCAS), pp.1-4, Seoul August 2011. DOI: 10.1109/MWSCAS.2011.6026572
- “Carbon nanotube growth process-related variability in CNFETs”
- C. García and A. Rubio, “Carbon nanotube growth process-related variability in CNFETs”, IEEE NANO 2011, August 15-19, pp- 1084-1087, Portland, Oregon. DOI: 10.1109/NANO.2011.6144375
- “Adaptive Fault-Tolerant Architecture for Unreliable Device Technologies”
- N. Aymerich, S. Cotofana, A. Rubio, “Adaptive Fault-Tolerant Architecture for Unreliable Device Technologies”, IEEE NANO 2011, August 15-19, pp. 1441-1444, Portland, Oregon. DOI: 10.1109/NANO.2011.6144528
- “TRAMS: Variability as a limiting factor of energy efficiency”
- A.Rubio, A. Asenov. “TRAMS: Variability as a limiting factor of energy efficiency”, Workshop on Energy Efficient Systems, Barcelona, July 18th, 2011.
- "Low Power Microarchitectures, tools for power/reliability simulation/estimation"
- Summer school, lecturer "Low Power Microarchitectures, tools for power/reliability simulation/estimation" ARCHI'11 (École thématique), Mont-Louis, France, June 2011
- "Variability and technology aware SRAM Product yield maximization"
- P. Zuber, M. Miranda, et al. "Variability and technology aware SRAM Product yield maximization". Intl. Symp. on VLSI Technology, Kyoto, Japan, June 2011, pp. 222-223. ISBN 978-1-4244-9949-6 (IEEE Xplore)
- “Device Variability Analysis in Carbon Nanotube Technology”
- García, C., Rubio, A., “Device Variability Analysis in Carbon Nanotube Technology”, 2nd European Workshop on Variability, Grenoble, May 2011
- “DEVICE TO PRODUCT LEVEL ASSESSMENT OF PROCESS VARIABILITY”
- Miguel Miranda. “DEVICE TO PRODUCT LEVEL ASSESSMENT OF PROCESS VARIABILITY”, Invited - 2nd European Workshop on Variability, Grenoble, May 2011
- “TRAMS : Terascale reliable adaptive memory systems”
- Canal, R.; Rubio, A.; Asenov, A.; Brown, A.; Miranda Corbalan, M.; Zuber, P.; Dobrovolny, P.; Gonzales, A. and Vera, X., (TRAMS) “TRAMS : Terascale reliable adaptive memory systems”, FET'11, The European Future Technologies Conference and Exhibition, Budapest, Hungary, May 2011, also SciVerse ScienceDirect, Procedia Computer Science 7 (2011) 148-149. DOI: 10.1016/j.procs.2011.09.010
- “Statistical Analysis of 6T SRAM Data Retention Voltage under Process Variation”
- Vatajelu, E., Figueras, J., “Statistical Analysis of 6T SRAM Data Retention Voltage under Process Variation”, 14th IEEE Design and Diagnostics of Electronic Circuits and Systems, pp. 365-370, 13-15 April 2011, Cottbus, Germany. DOI: 10.1109/DDECS.2011.5783112
- "Invited talk at HiPEAC Computing SystemsWeek, Task Force on Reliability and Availability"
- Invited talk at HiPEAC Computing SystemsWeek, Task Force on Reliability and Availability Chamonix, France , April 2011
- "Manufacturing Variability Analysis in Carbon Nanotube Technology: comparison with bulk CMOS in 6T SRAM scenario"
- C. Garcia and A. Rubio, "Manufacturing Variability Analysis in Carbon Nanotube Technology: comparison with bulk CMOS in 6T SRAM scenario", 14th IEEE Symposium on Design and Diagnosis of Electronic Circuits and Systems, pp. 249-254, Germany, April 13rd-14th 2011. DOI: 10.1109/DDECS.2011.5783088
- “Drain current collapse in nanoscaled bulk MOSFETs due to random dopant compensation in the source/drain extensions”
- S. Markov, X. Wang, N. Moezi and A. Asenov, “Drain current collapse in nanoscaled bulk MOSFETs due to random dopant compensation in the source/drain extensions”. IEEE Transactions on Electron Devices, vol.58, nº8, pp.2385-2393, 2011. DOI: 10.1109/TED.2011.2152845
- “Variability aware modelling for yield enhancement of SRAM and logic"
- Miranda Corbalan, M.; Zuber, P.; Dobrovolny, P. and Roussel, P., “Variability aware modelling for yield enhancement of SRAM and logic", IEEE Design Automation and Test In Europe Conference – DATE, Grenoble, France, March 2011, pp. 1153-1158. DOI: 10.1109/DATE.2011.5763193
- “Statistical aspects of NBTI/PBTI and impact on SRAM yield”
- A. Asenov, A. R. Brown and B. Cheng, “Statistical aspects of NBTI/PBTI and impact on SRAM yield”, IEEE Design, Automation and Test in Europe (DATE), Grenoble, France, March 2011. DOI: 10.1109/DATE.2011.5763240
- “A new probabilistic design methodology of nanoscale digital circuits”
- “A new probabilistic design methodology of nanoscale digital circuits”. 21st Int. Conference on Communications and Computers (CONIELECOMP), March 2011, pp. 190-193.
- "Runtime Monitoring of Power/Performance of Caches under Variability using Embedded 3T1D Cells”
- Shrikanth Ganapathy, Ramon Canal, Antonio González, Antonio Rubio, “Runtime Monitoring of Power/Performance of Caches under Variability using Embedded 3T1D Cells”. 2011 ACM/EDAC/IEEE Design and Automation Conference.
- "Robustness Analysis of 6T SRAMs in Memory Retention Mode under PVT Variations"
- E I Vatajelu and J Figueras, "Robustness Analysis of 6T SRAMs in Memory Retention Mode under PVT Variations," in Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011 , pp.1-6, 14-18 March 2011. DOI: 10.1109/DATE.2011.5763159
- “Analysis of the mismatch of digital circuits by common environment fluctuations”
- D. Andrade, A. Rubio, et al.“Analysis of the mismatch of digital circuits by common environment fluctuations”, Proc. IEEE Int. Symp. Circuits and Systems, ISCAS, 15-18th May, Rio de Janeiro, 2011, pp. 2585-2588. DOI: 10.1109/ISCAS.2011.5938133
- "New reliability mechanisms in memory design for sub-22nm technologies”
- N. Aymerich, A. Asenov, A. Brown, R. Canal, B. Cheng, J. Figueras, A. Gonzalez, E. Herrero, S. Markov, M. Miranda, P. Pouyan, T. Ramirez, A. Rubio, I. Vatajelu, X. Vera, X. Wang, P. Zuber; "New reliability mechanisms in memory design for sub-22nm technologies”, (invited paper) 17th IEEE On-Line Testing Symposium (IOLTS'11), Athens (Greece), July 2011. DOI: 10.1109/IOLTS.2011.5993820
- “Unidirectional error detection, localization and correction for DRAMs: Application to on-line DRAM repair strategies”
- Madalin, N., Miclea, L, Figueras, J., “Unidirectional error detection, localization and correction for DRAMs: Application to on-line DRAM repair strategies”, 17th Int. Symp. On line testinh (IOLTS), 2011 IEEE, pp. 264-269.
- “Fault Tolerant Nanoscale Architecture based on Linear Threshold gates, with redundancy”
- Aymerich, N., Rubio, A., “Fault Tolerant Nanoscale Architecture based on Linear Threshold gates, with redundancy”. Proc. Design of Electronic Circuits and Systems, October 2010.
- "Robustness of SRAM to Power Supply Noise during Leakage Power Saving in DVS"
- E. I. Vatajelu, M. Renovell, J. Figueras, "Robustness of SRAM to Power Supply Noise during Leakage Power Saving in DVS". Workshop on LPonTR, 2010
- “Design of Boolean functions and memory units based on Resistive Switching devices”
- García, C., Moll, F., Rubio., “Design of Boolean functions and memory units based on Resistive Switching devices”, Proc. Design of Electronic Circuits and Systems, October 2010.
- “Impact of metal gate granularity on the statistical variability in scaled decananometre bulk MOSFETs: A full-scale 3D simulation study”
- X. Wang, “Impact of metal gate granularity on the statistical variability in scaled decananometre bulk MOSFETs: A full-scale 3D simulation study”. et al. IEEE Trans. Electron Devices, submitted.
- “Simulation of statistical variability in 18 and 13nm bulk MOSFETs”
- A. R. Brown, “Simulation of statistical variability in 18 and 13nm bulk MOSFETs”. et al. Intel European Research and Innovation Conference, Leixlip, Ireland, October 2010
- “Electronic design paradigms in the technologies of the year 2020”
- C. Garcia, F. Moll and A. Rubio, “Electronic system design paradigms in the technologies of the year 2020”, Int. Soc. Mater. Eng. Resour. Vol. 17, No. 2, (Sept. 2010) DOI: 10.5188/ijsmer.17.87
- "TCAD simulation of statistical variability"
- A. R. Brown, "TCAD simulation of statistical variability" at Workshop on Simulation and Characterization of Statistical CMOS Variability and Reliability, Bologna (September 2010). DOI: No identifier
- "Cache Design Under Spatio-Temporal Variability"
- S. Ganapathy, R. Canal, A. González, A. Rubio, "Cache Design Under Spatio-Temporal Variability", Intel 2010 European Research and Innovation Conference, Braunschweig (Germany), September 2010
- "MODEST : A Model for Energy Estimation under Spatio-Temporal Variability"
- S. Ganapathy, R. Canal, A. González, A. Rubio, "MODEST : A Model for Energy Estimation under Spatio-Temporal Variability", Proc. of the IEEE Low Power Electronics and Design International Symposium (ISLPED), pp. 129-134, August 2010. DOI: 10.1145/1840845.1840873
- “A comprehensive compensation technique for process variations and environmental fluctuations in digital integrated circuits”
- D. Andrade, A. Calomarde, S.D. Cotofana and A. Rubio. “A comprehensive compensation technique for process variations and environmental fluctuations in digital integrated circuits.”, IEEE Proceedings on Midwest Symposium of Circuit and Systems, pp. 630-634, August 2010. DOI: 10.1109/MWSCAS.2010.5548578
- ”Turtle Logic: a new design metholodology of nanoscale digital circuits”
- García, L..; Calomarde, A.; Moll, F. & Rubio, A.,”Turtle Logic: a new design metholodology of nanoscale digital circuits”. IEEE Proceedings on Midwest Symposium of Circuit and Systems, pp. 422-426, August 2010. DOI: 10.1109/MWSCAS.2010.5548845
- ”Turtle: a new design metholodology for high noise low signal level scenarios.”
- García, L..; Calomarde, A.; Moll, F. & Rubio. "Turtle: a new design metholodology for high noise low signal level scenarios.”, A. IEEE Proceedings on Midwest Symposium of Circuit and Systems, August 2010.
- “A holistic approach for statistical analysis of SRAM”
- Zuber, P.; Dobrovolny, P. and Miranda Corbalan, M., “A holistic approach for statistical analysis of SRAM”. Proceedings of the 47th ACM/IEEE Design Automation Conference ‐ DAC. 13‐18 July 2010; Anaheim, CA, USA, pp.717-724. ISBN: 978-1-4244-6677-1 (IEEE Xplore)
- “Statistical SRAM analysis for yield enhancement”
- Zuber, P.; Miranda Corbalan, M.; Dobrovolny, P.; van der Zanden, K. and Jung, J., “Statistical SRAM analysis for yield enhancement”. Design, Automation and Test in Europe Conference ‐ DATE. 8‐12 March 2010; Dresden, Germany 2010, pp.57-62. ISBN: 978-3-9810801-6-2
- "Circuit Propagation Delay Estimation Through Multivariate Regression-Based Modeling Under Spatio-Temporal Variability"
- S. Ganapathy, R. Canal, A. González, A. Rubio. "Circuit Propagation Delay Estimation Through Multivariate Regression-Based Modeling Under Spatio-Temporal Variability." Proc. of the IEEE Design Automation and Test in Europe Conference (DATE), pp.417-422, March 2010 (Dresden, Germany). DOI: 10.1109/DATE.2010.5457167
- "Parametric Failure Analysis of Embedded SRAMs using Fast & Accurate Dynamic Analysis"
- E. I. Vatajelu, G. Panagopoulos, K. Roy, J. Figueras. "Parametric Failure Analysis of Embedded SRAMs using Fast & Accurate Dynamic Analysis". IEEE ETS 2010, pp 69-74. DOI: 10.1109/ETSYM.2010.5512778
- "Statistical Analysis of SRAM Parametric Failure under Supply Voltage Scaling"
- E. I. Vatajelu, J. Figueras, "Statistical Analysis of SRAM Parametric Failure under Supply Voltage Scaling". IEEE AQTR 2010, pp. 1-6. DOI: 10.1109/AQTR.2010.5520825