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PDK FOR SUB 16 NM TECHNOLOGY BULK MOSFETS INCLUDING STATISTICAL VARIABILITY AND STATISTICAL RELIABILITY
Located in Publications / Project leaflets and posters
IMPACT OF VARIABILITY AND RELIABILITY ON SUB-18nm RAM MEMORIES
Located in Publications / Project leaflets and posters
TRAMS intranet manual
Located in Publications
N. Aymerich, S. Cotofana, A. Rubio, “Controlled degradation stochastic resonance in adaptive averaging cell based architectures”, IEEE Transactions on Nanotechnology (invited, accepted), 2013.
Located in Publications
P. Pouyan, E. Amat, A. Rubio, “Design and implementation of an adaptive proactive reconfiguration technique in SRAM caches”, DATE 2013 (accepted)
Located in Publications
J. Carretero, E. Herrero, M. Monchiero, T. Ramirez, X. Vera, “Capturing vulnerability variations for register files”, DATE 2013 (accepted)
Located in Publications
V. Lorente et al., “Combining RAM technologies for hard-error recovery in L1 data caches working at very low power modes”, DATE 2013 (accepted)
Located in Publications
Z. Jaksic, R. Canal, “Comparison of SRAM cells for 10nm SOI FinFETs under process and environmental variations”, IEEE Transactions on Electron Devices, vol.6, no.1, pp. 49-55, January 2013. DOI: 10.1109/TED.2012.2226095
Located in Publications
E. Amat et al., “Impact of FinFET technology introduction in the 3T1D-DRAM memory cell”, submitted to IEEE Transactions on Devices and Materials Reliability. DOI: 10.1109/TDMR.2013.2238542
Located in Publications
E. Amat, et al., “Variability mitigation mechanisms in scaled 3T1D-DRAM memories in 22nm and beyond”, IEEE Transactions on Devices and Materials Reliability, (accepted) 2013. DOI: 10.1109/TDMR.2012.2217497
Located in Publications