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Concept and project objectives

   Information technology is at the core of our society and it relies completely on the design of electronic information processing systems. The constant evolution of these systems depends on the continued enhancement and refinement of the silicon MOS fabrication technology. For more than three decades, industry has been able to roughly double the device density every two years following Moore’s law; however, future device integration technology is expected to dramatically reduce the device quality, and therefore the operation reliability of circuits.

   The great challenge for future technologies is building reliable systems on top of unreliable components, which will degrade and even fail during the normal lifetime of the chip. Devising new approaches so that future integrated circuits (and especially microprocessors) are resilient to lifetime degradation in a transparent manner for the users is becoming a requirement.

   In future tera-device multicore microprocessors, as defined by the industry roadmaps, the memories pay an extremely important role to achieve the desired performance. In a multicore architecture, cores may have different failure rates due to process variations. Additionally, core workload expectations can shift dynamically at run-time and each core may degrade differently based on its usage. Therefore, we expect user requirements beyond 2020 to be along the traditional axis of performance, the emerging axis of low power and the new axis of reliability.
Fig. 1.1 The TRAMS vision for reliable, cost-efficient tera-device multicores powering high performance future, safety-critical applications
   The TRAMS project will address the high performance and low power tera-device multicore requirements, while focusing on the new reliability requirement arising from issues as Negative Bias Temperature Instability (NBTI), Hot Carrier Degradation (HCD), Time Dependent Dielectric Breakdown due to aggressive technology scaling (i.e., below 10nm technology node) and novel device types (i.e., FinFET, III-V/Ge and CarbonNanoTubes). In this way, the TRAMS project addresses in an evolutionary way the ultimate CMOS scaling technologies and paves the way for revolutionary, most promising beyond-CMOS technologies.

   To achieve these very ambitious targets, the TRAMS project will model and analyse the variability and reliability issues from the technology to the circuit level. This information will be leveraged to develop new structures, innovative monitoring and countermeasure mechanisms at the circuit, micro-architectural and system level mitigating variability and improving reliability. The TRAMS countermeasure mechanisms will be cost-efficient, avoiding hardware oversizing and other worst-case design solutions. Instead, TRAMS will reconfigure the multicore components and the system dynamically at run-time, as needed, using hybrid software and hardware countermeasure mechanisms. The application focus of TRAMS is the memory subsystem for tera-device multicores in the personal computing and server domain, enabling reliable and cost-efficient ambitious applications based on the grid and cloud computing model.

B 1.1.1 Project objectives and expected results:

The objectives of the TRAMS project are:

1. To investigate the impact of statistical variability and reliability of near and beyond the end of the ITRS devices on terabit memory design.

   Workpackage 1 (WP1) and 2 (WP2) will be devoted to this general objective, where the key steps of research will be:

  •    To define the design and structure of bulk, FinFET, III-V/Ge and nanowire/CNT devices which are the 4 pillars of TRAMS
  •    To extract nominal compact models for the above devices.
  •    To simulate the initial variability and the additional variability introduced by aging.
  •    To extract statistical compact models of fresh and degraded devices.
  •    All these objectives are inside WP1, results are expected to be delivered at M12 (D1.1), M18 (D1.2), M27 (D1.3) and M36 (D1.4).
  •    The overall objective of WP2 is to develop a method for a prototype tool flow for Variability and Reliability Aware modelling of SRAM blocks for the different technologies of the four pillars (i.e., single bulk CMOS, FinFET, IIIVGe, CNT).
2. To design, implement, deploy and assess compensating techniques and countermeasures at circuit and microarchitecture level for memories used in multicore processors.

   Workpackage 3 (WP3) and partially 4 (WP4) will be devoted to this general objective, where the key steps of research will be:

  •    Research and development of mitigating mechanisms and strategies to reduce variability and increase reliability at layout and circuit level.
  •    Development of a method and prototype tool flow for run-time timing monitoring and switchable buffer insertion in SRAMs as hardware countermeasures at the circuit level.
  •    Research on the effect of environmental deviations (temperature, time violation, noise level, current level, voltage level, energy consumption), on the performances of the SRAM system. Different SRAM and processing cell structures will be considered putting special emphasis on new cell structures.
  •    Research on compensating mechanisms as well as redundant structures in the processing memory blocks considering the environmental parameters, process variability and the reliability predictions obtained in WP1 and 2.
  •    Develop mixed run-time methodologies to predict memory faulty behaviour

   All these objectives are inside WP3 and WP4, results are expected to be delivered at M12 (D3.1, D4.1), M24 (D3.2, D3.3, D3.4, D4.2, D4.3) and M36 (D3.5, D3.6, D4.1, D4.2, D4.3).

3. To develop a methodology for specifying and implementing performance-, power- and reliability-aware reconfiguration policies for multicore processor.

Workpackage 4 is fully devoted to this objective. The key research topics will be:

  •     Develop run-time methodologies to identify program memory requirements in terms of correctness, performance and power. We will focus on caches (shared and private) and register files.
  •     Develop run-time decision mechanisms that will find the best memory configurations that adapt to program requirements in terms of correctness, performance and power. Focus on will be apply to caches (shared and private) and register files.
  •     Based on the information provided by the other tasks, we will devise a methodology that will control the multicore processor and reconfigure it to obtain the best configuration in terms of performance and power. Actions may include test allocation, DVFS, issue throttling, thread allocation, memory reconfiguration, etc, etc.
   Results are expected to be delivered at M12 (D4.1.1), M24 (D4.1.2, D4.2.1, D4.3.1, D4.4.1) and M36 (D4.1.3, D4.2.2, D4.3.2, D4.4.2)

In order to accomplish these objectives, the TRAMS project will focus on:

  •    Providing a Preliminary Design Kit (PDK) for a representative selection of potential post 16nm devices including bulk 13 and 9 nm MOSFETs, sub 10nm FinFETs,  and 15nm III-V/Ge CMOS co-integration, and nanowire/CNT devices including statistical variability and reliability.
  •    Assessing the impact of variations and degradation on memory performance, power and reliability.
  •    Providing automatic reconfiguration policies which will match the user requirements in terms of performance, power and reliability.
The approach proposed by the TRAMS consortium includes:

  •    Development of a set of techniques at both circuit and microarchitecture level that detect malfunctioning parts.
  •    Development of a set of techniques at both circuit and microarchitecture level that mitigate variability and increase the reliability of memory cells.
  •    Development of a runtime program analysis that allows identifying the program characteristics that impact performance, power and reliability.
  •    Definition of reconfiguration policies that based on the user requirements and program characteristics, reconfigure the multicore system using the mitigation techniques previously developed.

   The target system will be multicore architectures with multiple on-chip levels of cache memories. Examples of these architectures are the Polaris prototype from Intel®, and the Niagara processor from Sun Microsystems.

   The project will aim at reaching the user requirements, which may vary between a specified performance, power consumption or required reliability, and adapt the multicore memory structures (i.e., register files and caches) to obtain such requirement.

   In order to facilitate the dissemination of results, TRAMS will use standard CAD tools at all levels and the GEMS toolset to evaluate the final multicore system. At the same time, TRAMS will be using standard device simulation modelling, and standard description at circuit, logic and system levels. This way, we will achieve an optimum impact and dissemination of the activities of the project beyond the consortium.