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D. Rodopoulos, A. Papanikolaou and F. Catthoor, "Software Mitigation of Transient Errors on the Single-Chip Cloud Computer", in IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE), Urbana-Champaign, IL, US, 2012.
Located in Publications
E. I. Vatajelu, J. Figueras, “Efficiency Evaluation of Parametric Failure Mitigation Techiques for Reliable SRAM Operation”, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012, pp. 1343-1348. DOI: 10.1109/DATE.2012.6176700
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V. Lorente et al., “Combining RAM technologies for hard-error recovery in L1 data caches working at very low power modes”, DATE 2013 (accepted)
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J. Carretero, E. Herrero, M. Monchiero, T. Ramirez, X. Vera, “Capturing vulnerability variations for register files”, DATE 2013 (accepted)
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P. Pouyan, E. Amat, A. Rubio, “Design and implementation of an adaptive proactive reconfiguration technique in SRAM caches”, DATE 2013 (accepted)
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A. Asenov, A. R. Brown and B. Cheng, “Statistical aspects of NBTI/PBTI and impact on SRAM yield”, IEEE Design, Automation and Test in Europe (DATE), Grenoble, France, March 2011. DOI: 10.1109/DATE.2011.5763240
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Miranda Corbalan, M.; Zuber, P.; Dobrovolny, P. and Roussel, P., “Variability aware modelling for yield enhancement of SRAM and logic", IEEE Design Automation and Test In Europe Conference – DATE, Grenoble, France, March 2011, pp. 1153-1158. DOI: 10.1109/DATE.2011.5763193
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Canal, R.; Rubio, A.; Asenov, A.; Brown, A.; Miranda Corbalan, M.; Zuber, P.; Dobrovolny, P.; Gonzales, A. and Vera, X., (TRAMS) “TRAMS : Terascale reliable adaptive memory systems”, FET'11, The European Future Technologies Conference and Exhibition, Budapest, Hungary, May 2011, also SciVerse ScienceDirect, Procedia Computer Science 7 (2011) 148-149. DOI: 10.1016/j.procs.2011.09.010
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García, L..; Calomarde, A.; Moll, F. & Rubio, A.,”Turtle Logic: a new design metholodology of nanoscale digital circuits”. IEEE Proceedings on Midwest Symposium of Circuit and Systems, pp. 422-426, August 2010. DOI: 10.1109/MWSCAS.2010.5548845
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N. Nivard, R. Canal, A. Gonzalez, A. Rubio, “Impact of positive temperature instability on 3T1D DRAM cells integration”, VLSI Journal Integration, 45-3, pp. 246-252, 2012. DOI: 10.1016/j.vlsi.2011.11.014
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