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C. García, A. Rubio, “Variability and reliability analysis of CNFET in the presence of carbon nanotube density fluctuations”, Proceedings of the MIXDES Conference, 2012, 24th-26th May, Warsaw,pp.124-129. ISBN 978-1-4577-2092-5 (IEEE Xplore)
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P. Peyman et al., “SRAM lifetime improvement by using adaptive proactive reconfiguration”, MIXDES 2012, 24th-26th May, Warsaw, pp. 115-119. ISBN 978-1-4577-2092-5 (IEEE Xplore)
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P. Peyman, A. Rubio, “Process variability-aware proactive reconfiguration techniques for mitigating aging effects in nano scale SRAM lifetime”, IEEE VLSI Test Symposium (VTS), Hawaii, May 2012, pp.240-245. DOI: 10.1109/VTS.2012.6231060
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N. Aymerich, S. Cotofana, A. Rubio, “Degradation Stochastic Resonance (DSR) in AD-AVG architectures”, IEEE Nano 2012, Birmingham, 2012, pp. 1-4. DOI: 10.1109/NANO.2012.6321971
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X. Vera, “DFH(eterogeneity) for tera-scale reliable processors”, IEEE LSI Test Symposium (VTS), Hawaii, May 2012. DOI: 10.1109/VTS.2012.6231108
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T. Ramírez at al., “Mitigating lower layer failures with adaptive system reconfiguration” MIXDES 2012, 24th-26th May, Warsaw. ISBN 978-1-4577-2092-5 (IEEE Xplore)
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Z. Jaksic et al., “Enhancing 6T SRAM cell stability by back gate biasing techniques for 10nm SOI Finfets under process and environmental variations”, MIXDES 2012, 24th-26th May, Warsaw, pp. 103-108. ISBN 978-1-4577-2092-5 (IEEE Xplore)
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E. Amat, et al., “Strain relevance on the improvement of the 3T1D cell performance” MIXDES 2012, 24th-26th May, Warsaw. pp. 120-123. ISBN 978-1-4577-2092-5 (IEEE Xplore)
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L. García-Leyva., et al., “New redundant logic design concept for high noise and low voltage scenarios”, Microelectronics Journal, 42 (2011), pp. 1359-1369. DOI: 10.1016/j.mejo.2011.09.007
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N. Aymerich, S. Ganapathy, A. Rubio, R. Canal, A. González, “Impact of positive bias temperatura instability (PBTI) on 3T1D-DRAM cells”, IEEE/ACM Great Lakes Symposium on VLSI, Lausanne (Switzerland), May 2011. DOI 10.1016/j.vlsi.2011.11.014
Located in Publications