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"Manufacturing Variability Analysis in Carbon Nanotube Technology: comparison with bulk CMOS in 6T SRAM scenario"
C. Garcia and A. Rubio, "Manufacturing Variability Analysis in Carbon Nanotube Technology: comparison with bulk CMOS in 6T SRAM scenario", 14th IEEE Symposium on Design and Diagnosis of Electronic Circuits and Systems, pp. 249-254, Germany, April 13rd-14th 2011. DOI: 10.1109/DDECS.2011.5783088
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S. Ganapathy, R. Canal, A. González, A. Rubio, "MODEST : A Model for Energy Estimation under Spatio-Temporal Variability", Proc. of the IEEE Low Power Electronics and Design International Symposium (ISLPED), pp. 129-134, August 2010. DOI: 10.1145/1840845.1840873
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N. Aymerich, A. Asenov, A. Brown, R. Canal, B. Cheng, J. Figueras, A. Gonzalez, E. Herrero, S. Markov, M. Miranda, P. Pouyan, T. Ramirez, A. Rubio, I. Vatajelu, X. Vera, X. Wang, P. Zuber; "New reliability mechanisms in memory design for sub-22nm technologies”, (invited paper) 17th IEEE On-Line Testing Symposium (IOLTS'11), Athens (Greece), July 2011. DOI: 10.1109/IOLTS.2011.5993820
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E. I. Vatajelu, G. Panagopoulos, K. Roy, J. Figueras. "Parametric Failure Analysis of Embedded SRAMs using Fast & Accurate Dynamic Analysis". IEEE ETS 2010, pp 69-74. DOI: 10.1109/ETSYM.2010.5512778
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E I Vatajelu and J Figueras, "Robustness Analysis of 6T SRAMs in Memory Retention Mode under PVT Variations," in Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011 , pp.1-6, 14-18 March 2011. DOI: 10.1109/DATE.2011.5763159
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E. I. Vatajelu, M. Renovell, J. Figueras, "Robustness of SRAM to Power Supply Noise during Leakage Power Saving in DVS". Workshop on LPonTR, 2010
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"Runtime Monitoring of Power/Performance of Caches under Variability using Embedded 3T1D Cells”
Shrikanth Ganapathy, Ramon Canal, Antonio González, Antonio Rubio, “Runtime Monitoring of Power/Performance of Caches under Variability using Embedded 3T1D Cells”. 2011 ACM/EDAC/IEEE Design and Automation Conference.
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D. Rodopoulos, A. Papanikolaou and F. Catthoor, "Software Mitigation of Transient Errors on the Single-Chip Cloud Computer", in IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE), Urbana-Champaign, IL, US, 2012.
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E. I. Vatajelu, J. Figueras, "Statistical Analysis of SRAM Parametric Failure under Supply Voltage Scaling". IEEE AQTR 2010, pp. 1-6. DOI: 10.1109/AQTR.2010.5520825
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X. Wang, A. R. Brown, N. M. Idris, S. Markov, G. Roy, and A. Asenov, "Statistical threshold-voltage variability in scaled decananometer bulk HKMG MOSFETs: A full-scale 3-D simulation scaling study". IEEE Transactions on Electron Devices, Vol. 58, No. 8, pp. 2293–2301, 2011. DOI: 10.1109/TED.2011.2149531
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