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García, C., Rubio, A., “Device Variability Analysis in Carbon Nanotube Technology”, 2nd European Workshop on Variability, Grenoble, May 2011
Located in Publications
X. Vera, “DFH(eterogeneity) for tera-scale reliable processors”, IEEE LSI Test Symposium (VTS), Hawaii, May 2012. DOI: 10.1109/VTS.2012.6231108
Located in Publications
S. Markov, X. Wang, N. Moezi and A. Asenov, “Drain current collapse in nanoscaled bulk MOSFETs due to random dopant compensation in the source/drain extensions”. IEEE Transactions on Electron Devices, vol.58, nº8, pp.2385-2393, 2011. DOI: 10.1109/TED.2011.2152845
Located in Publications
“Drain current collapse in nano-scaled bulk MOSFETs due to random dopant compensation in the source/drain extensions”
S. Markov, X.Wang, N.Moezi and A.Asenov. “Drain current collapse in nano-scaled bulk MOSFETs due to random dopant compensation in the source/drain extensions”. IEEE Transactions on Electron Devices, Vol. 58, Nº8, pp.2385-2393, 2011. DOI: 10.1109/TED.2011.2152845
Located in Publications / retirados
S. Ganapathy, R. Canal, A. González, A. Rubio. “Dynamic Fine-Grain Body Biasing of Caches with Latency and Leakage 3T1D-Based Monitors”. 29th IEEE International Conference on Computer Design (ICCD'11), Amherst (MA, USA), October 2011, pp. 332-338. DOI: 10.1109/ICCD.2011.6081420
Located in Publications
E. I. Vatajelu, J. Figueras, “Efficiency Evaluation of Parametric Failure Mitigation Techiques for Reliable SRAM Operation”, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012, pp. 1343-1348. DOI: 10.1109/DATE.2012.6176700
Located in Publications
“Electronic design paradigms in the technologies of the year 2020”
C. Garcia, F. Moll and A. Rubio, “Electronic system design paradigms in the technologies of the year 2020”, Int. Soc. Mater. Eng. Resour. Vol. 17, No. 2, (Sept. 2010) DOI: 10.5188/ijsmer.17.87
Located in Publications
Z. Jaksic et al., “Enhancing 6T SRAM cell stability by back gate biasing techniques for 10nm SOI Finfets under process and environmental variations”, MIXDES 2012, 24th-26th May, Warsaw, pp. 103-108. ISBN 978-1-4577-2092-5 (IEEE Xplore)
Located in Publications
“Fault Tolerant Nanoscale Architecture based on Linear Threshold gates, with redundancy”
Aymerich, N., Rubio, A., “Fault Tolerant Nanoscale Architecture based on Linear Threshold gates, with redundancy”. Proc. Design of Electronic Circuits and Systems, October 2010.
Located in Publications
N. Aymerich, R.Canal, A.Gonzalez, A. Rubio, “Fault-tolerant nanoscale architecture based on linear threshold gates with redundancy” Microprocessors and Microprosystems, volumen 36, issue 5, July 2012, pp. 420-426, DOI 10.1016/j.micpro.2012.02.003
Located in Publications