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E. Amat et al., “Impact bulk/SOI 10nm FinFETs on 3T1D-DRAM cell performance” 11th IEEE Int. Conf. on Solid-State and Integrated Circuits Technology (ICSICT), 2012, Xi’an, China.
Located in Publications
E. Amat et al., “Impact of FinFET technology introduction in the 3T1D-DRAM memory cell”, submitted to IEEE Transactions on Devices and Materials Reliability. DOI: 10.1109/TDMR.2013.2238542
Located in Publications
X. Wang, “Impact of metal gate granularity on the statistical variability in scaled decananometre bulk MOSFETs: A full-scale 3D simulation study”. et al. IEEE Trans. Electron Devices, submitted.
Located in Publications
“Impact of metal gate granularity on the statistical variability in scaled decananometre bulk MOSFETs: A full-scale 3D simulation study”
X. Wang, “Impact of metal gate granularity on the statistical variability in scaled decananometre bulk MOSFETs: A full-scale 3D simulation study”. et al. IEEE Trans. Electron Devices, submitted.
Located in Publications / retirados
N. Aymerich, S. Ganapathy, A. Rubio, R. Canal, A. González, “Impact of positive bias temperatura instability (PBTI) on 3T1D-DRAM cells”, IEEE/ACM Great Lakes Symposium on VLSI, Lausanne (Switzerland), May 2011. DOI 10.1016/j.vlsi.2011.11.014
Located in Publications
N. Nivard, R. Canal, A. Gonzalez, A. Rubio, “Impact of positive temperature instability on 3T1D DRAM cells integration”, VLSI Journal Integration, 45-3, pp. 246-252, 2012. DOI: 10.1016/j.vlsi.2011.11.014
Located in Publications
T. Ramírez at al., “Mitigating lower layer failures with adaptive system reconfiguration” MIXDES 2012, 24th-26th May, Warsaw. ISBN 978-1-4577-2092-5 (IEEE Xplore)
Located in Publications
M. Neagu, L. Miclea, “Modified Berger codes for on-line DRAM repair strategies”, IEEE AQTR, 2012, pp. 296-301. May 2012. DOI: 10.1109/AQTR.2012.6237720
Located in Publications
L. García-Leyva., et al., “New redundant logic design concept for high noise and low voltage scenarios”, Microelectronics Journal, 42 (2011), pp. 1359-1369. DOI: 10.1016/j.mejo.2011.09.007
Located in Publications
P. Peyman, A. Rubio, “Process variability-aware proactive reconfiguration techniques for mitigating aging effects in nano scale SRAM lifetime”, IEEE VLSI Test Symposium (VTS), Hawaii, May 2012, pp.240-245. DOI: 10.1109/VTS.2012.6231060
Located in Publications